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T3347B
T3326A/T3347A

VLSI Test System
Low-cost Parallel Testing of Four High-end MCU and Testing of Large ASIC F5112
The 3347B was developed to achieve low-cost testing of 16/32-bit MCU and of large-scale ASIC based on such processors. The cost-of-ownership concept employed in the development of these systems was aimed at providing improved throughput, reduced space requirements, low power consumption, and better maintainability in comparison with previous systems. Specifications were established to reduce cost, and optimization of hardware was also achieved.

40 MHZ testing speed.
Accommodates up to 512 I/O pins.
Simultaneous testing of up to four devices per station.

. T3347B
Target Devices High-pincount gate arrays, ASIC, CBIC, ASSP
Test Speed 20/40 MHz(multiplex mode)/,40/80 MHz (multiplex mode,data rate)
Pin Configurations 512 I/O pins
Overall Timing Accuracy ¡Ó2.0 ns/¡Ó1.6 ns (HV2 head)
Simultaneous Testing Up to 4 per test head
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